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7 Software interface
The following section describes the hardware registers used by the host software to issue commands to the
Drive.
7.1 ATA Drive Register Set Definition and Protocol
The drive can be used as a high performance I/O device through:
Standard PC-AT disk I/O address spaces
o
o
1F0h-1F7h, 3F6h-3F7h (primary);
170h-177h, 376h-377h (secondary)
7.2 True IDE Mode Addressing
The Drive registers for reading and writing are specified in Table 27.
Table 27 : True IDE Mode I/O Decoding
- CS1
1
1
1
1
1
1
1
1
1
0
- CS0
0
1
0
0
0
0
0
0
0
1
A2
0
X
0
0
0
1
1
1
1
1
A1
0
X
0
1
1
0
0
1
1
1
A0
0
X
1
0
1
0
1
0
1
0
-DMACK
1
0
1
1
1
1
1
1
1
1
- IORD=0
PIO RD Data
DMA RD Data
Error Register
Sector Count
Sector No.
Cylinder Low
Cylinder High
Select Card/Head
Status
Alt Status
- IOWR=0
PIO WR Data
DMA WR Data
Features
Sector Count
Sector No.
Cylinder Low
Cylinder High
Select Card/Head
Command
Control Register
7.3 Data Register
The Data register is located at address 1F0h [170h], offset 0h, 8h, and 9h.
The Data Register is a 16 bit register used to transfer data blocks between the Drive data buffer and the
Host. This register overlaps the Error Register. Table 28 describes the combinations of Data register access
and explain the overlapped Data and Error/Feature Registers. Because of the overlapped registers, access to
the 1F1h, 171h or offset 1 are not defined for Word (-CS1 and – CS0 set to ‘0’) operations, and are treated as
accesses to the Word Data Register. The duplicated registers at offsets 8, 9 and Dh have no restrictions on
the operations that can be performed.
Table 28: Data Register Access (True IDE mode)
Data Register
PIO Word Data Register
DMA Word Data Register
PIO Byte Data Register (Selected Using Set
-CS1
1
1
1
-CS0
0
1
0
A0
0
X
0
-DMACK
1
0
1
Offset
0h
X
0h
Data Bus
D15 to D0
D15 to D0
D7 to D0
Features Command)
7.4 Error Register
The Error register is a read-only register, located at address 1F1h [171h], offset 1h, 0Dh.
This read only register contains additional information about the source of an error when an error is
indicated in bit 0 of the Status register. The bits are defined in Table 29 This register is accessed on data bits
D15 to D8 during a write operation to offset 0 with – CS1 Low and – CS0 High.
7.4.1 Bit 7 (BBK)
This bit is set when a Bad Block is detected.
7.4.2 Bit 6 (UNC)
This bit is set when an Uncorrectable Error is encountered.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
P-120_data_sheet_PA-QxBO_Rev100.doc
Page 32 of 76
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